This invention relates to a dynamic random-access memory device, more particularly to an improvement enabling higher levels of integration of memory cells comprising one transistor and one capacitor.
Dynamic random-access memory (DRAM) devices are being made with increasingly high densities of integration. In a DRAM, an information bit is stored as a capacitor charge in a memory cell usually comprising one capacitor and one transistor. An essential requirement for the attainment of extremely high integration densities is to reduce the size of this basic memory cell. In scaling down the cell size, however, it is necessary to maintain a certain minimum capacitance (generally considered to be 50 fF), because if the capacitance of the capacitor is too low, the circuit is susceptible to soft errors caused by alpha particles and to other malfunctions. Let C be the capacitance of the capacitor, T.sub.ox be the thickness of the silicon oxide (SiO.sub.2) film, .epsilon..sub.ox be its dielectric constant, and S be the capacitance surface area. Then the following relation is approximately true: EQU C=.epsilon..sub.OX S/T.sub.OX
As DRAM integration density increases, the size of the memory cell decreases. With a conventional planar memory cell structure, the capacitor area S decreases proportionately and the necessary value of C can only be maintained by reducing the silicon oxide thickness T.sub.OX, or increasing .epsilon..sub.OX by replacing silicon oxide with a material having a higher dielectric constant. Compensating for a reduced S by reducing T.sub.OX raises major problems, however. In to maintain the needed C, the silicon oxide must be made so thin that its dielectric breakdown voltage becomes inadequate and the incidence of structural defects rises. There are also problems in using dielectric materials with a higher dielectric constant than silicon oxide. Tantalum oxide (Ta.sub.2 O.sub.5) has been considered as a candidate material, but a method of forming the necessary Ta.sub.2 O.sub.5 films has not yet been established. Also, a high dielectric constant material is generally associated with a narrow band gap, which offers less resistance to current flow and allows increased leakage current, thereby degrading interface properties as compared with silicon oxide, and causing electrical instability and other problems. For these reasons, it appears difficult to replace silicon oxide with a different material. What is needed is therefore a memory cell structure that combines small cell size with large effective capacitor area.
For these reasons, megabit-class DRAMs have departed from the conventional two-dimensional planar memory-cell structure and begun using three-dimensional structures. Two examples of such three-dimensional structures are the stacked capacitor memory cell, in which the capacitor is stacked on top of the cell, and the trench capacitor memory cell, in which the capacitor is formed inside a trench in the semiconductor substrate. These structures enable a small memory cell to have a large effective capacitor area. In the stacked capacitor memory cell, shown in FIG. 2, the capacitor comprises a dielectric film 4 separating two polysilicon films: one acting as the charge storage electrode 5.sub.1 ; the other acting as the plate electrode 5.sub.2. The capacitor comprising these three films is stacked on top of a gate electrode 8 and a field oxide 2.sub.1, enabling a larger capacitor area, hence a greater capacitance, to be obtained than in a planar memory cell. Another advantage of this structure is that except at the contact 26 between the charge storage electrode 5.sub.1 and the diffusion region 9, the capacitor is separated from the silicon substrate, which reduces the susceptibility of the memory cell to alpha-particle-induced soft errors. A disadvantage of this structure as compared with the trench capacitor structure is that it offers less increase in effective capacitor area, permitting only a limited scaling down of memory cell size. Another disadvantage of a structure in which the capacitor is stacked on top of the memory cell is that the resulting surface unevenness presents an obstacle to fine patterning.
In the trench capacitor memory cell, shown in FIG. 3, the capacitor 13 is created in a trench 3 formed in a silicon substrate 1. A dielectric film 4 is grown on the inner surface of the trench 3, then the trench 3 is filled in with polysilicon which forms an electrode 5. Since the capacitor 13 is embedded in a trench 3, compensation for reduction in memory cell size can in principle be obtained by deepening the trench 3 to secure the surface area needed to maintain the required cell capacitance. The trench capacitor memory cell structure is thus advantageous for high levels of circuit integration.
A difficulty with the trench capacitor memory cell, however, is that the trenches of adjacent cells are not completely isolated from one another. If the trenches of adjacent capacitors are too closely spaced, so that their depletion layer approach too closely, leakage current tends to flow between the trenches, degrading such cell characteristics as maximum allowable voltage and charge retention. The trenches must therefore be kept a certain distance apart, placing a serious restriction on the scaling down of cell size. The trench spacing can be reduced if the silicon substrate is heavily doped with impurities to restrict extending of the depletion layer and block the flow of leakage current, but this method offers only a limited solution, because heavy doping also raises the threshold voltage of the transistors formed on the silicon substrate, so that their junction breakdown voltage becomes intolerably low. Another problem with this trench-capacitor memory cell structure is that it is inherently susceptible to alpha-particle-induced soft errors.
In summary, the stacked capacitor memory cell and trench capacitor memory cell of the prior art both offer advantages, but both also suffer from major disadvantages that limit the density of integration of the memory cells. A memory cell structure has been considered that combines the advantages of both by forming a PIP (Polysilicon-Insulator-polysilicon) capacitor of the type used in a stacked capacitor memory cell inside a trench. This memory cell structure, however, also has disadvantages. The scaling down of its size is limited by the need to form a thick oxide film inside the trench to isolate the lower electrode (the charge storage electrode) from the substrate, which tends to place stress on the trench silicon, and the need to open a contact hole at which the charge storage electrode can make contact with the substrate.